The invention relates to a PLL (phase-lock loop) circuit, and more particularly to a PLL circuit which can shorten lock-up time.
Shortening the lock-up time (or settling time) of a phase comparator circuit is required of PLL circuits used in ICs (or LSIs) of mobile radio equipment and the like. Shortened lock-up time (time elapsed until the frequency difference becomes zero (0)) can be achieved by increasing the band width of a loop filter. Increasing the loop band, however, poses problems of a deterioration in C/N (signal-to-noise ratio) at the output terminal of VCO (voltage controlled oscillator) and an increase in spurious harmonics. For example, Japanese Patent Laid-Open No. 215171/1998 discloses a PLL circuit for solving this problem. This PLL circuit will be explained in conjunction with FIG. 1.
An adder 102 is connected to a current output-type phase comparator (PD) 101 into which an input signal frequency fIF is input. A constant-current source 103, a reset switch 104, and a low pass filter (LPF) 105 are connected to the adder 102. VCO 106 for outputting a VCO output frequency fRF is connected to LPF 105. A coupler 107 is connected to this VCO 106, and a mixer 108, into which a local signal frequency fLO is input, is connected between the coupler 107 and PD 101. In this construction, PD 101, LPF 105, VCO 106, and the mixer 108 basically constitute the PLL circuit. This construction is characterized by providing a constant current source 103 and a reset switch 104. The constant current source 103 functions to apply constant current to LPF 105.
The operation of the PLL circuit shown in FIG. 1 will be explained. In PD 101, the phase of the input signal frequency fIF is compared with the phase of the reference signal frequency fRF, and a current proportional to the phase difference is output. When the PLL circuit is in a standby state, a reset switch 104 is turned ON, whereupon charges accumulated in a capacitor of LPF 105 are discharged, and VCO control voltage is brought to the ground state (0 V). During the operation of PLL, the reset switch 104 is turned OFF, and charges are accumulated in the capacitor within LPF 105 by a constant-current source 103 to increase the accumulation speed (to shorten the time elapsed until the VCO control voltage is increased from 0 V to a desired voltage). This can shorten the lock-up time.
In order to shorten the settling time of PLL, a constant current output from the constant current source 103 is added to the output current of PD 101, and the total current is input into LPF 105. In LPF 105, unnecessary harmonic components and noises in the input total current are removed, followed by conversion to DC voltage which is input into VCO 106. The output frequency fRF of VCO 106 is input into the mixer 108 through the coupler 107. A mixer 108 mixes an output frequency fRF with a local signal frequency fLO. The output frequency fREF of the mixer 108 is given by fREF=fLOxe2x88x92fRF. The output frequency fRF of the mixer, when PLL is locked, is equal to the input signal frequency fIF. Therefore, fIF is converted to fREF=fLOxe2x88x92fIF.
As described above, a direct current component of the output current from PD 101 accumulates charges in the capacitor of LPF 105, and the output voltage is input into VCO 105. At the same time, the constant current output from the constant current source 103 is also accumulated in the above capacitor. As a result, as compared with the case where the constant current source 103 is not provided. the accumulation speed of charges in the capacitor is increased. Therefore, the settling time of PLL is shortened.
Japanese Patent Laid-Open Nos. 288518/1988 and 259902/1993 propose a PLL circuit having a construction such that the time constant of LPF is variable and, at power-on time and at the time of becoming unlocked upon a change of the division ratio of a frequency divider, the time constant is changed and, after locking, the time constant is returned to the previous value.
According to the conventional PLL circuit, however, also when PLL is locked, the constant current source 103 is operated. In this case, when the set current of the constant current source 103 is excessive, an increase in output voltage of the phase comparator 101 is faster than the following of PLL per se and PLL is unlocked. Therefore, a limitation is imposed on current setting.
Further, since the constant current source is operated also when PLL is locked, the phase comparator 101 sometimes cannot maintain a phase difference of 90 degrees relative to two signals of input fIF and fREF. This poses a problem of an increase in noise and spurious harmonics on the output side.
The application of all the PLL circuits of the above-described publications to a digital system is contemplated, and these PLL circuits cannot be applied to an analog system having frequency width. That is, in the digital system, the use of a frequency divider, which is unnecessary in the analog system, is indispensable. Further, Japanese Patent Laid Open No. 288518/1988 does not show how to generate time constant switch signal output at the time of unlocking. In Japanese Patent Laid-Open No. 259902/1993, a division ratio is necessary in a computing equation for judging the phase difference, and, in this case, the use of a frequency divider, which is unnecessary in the analog system, is indispensable.
Accordingly, it is an object of the invention to provide a PLL circuit which can shorten the lock-up time of PLL of an analog system.
It is another object of the invention to provide a PLL circuit which, even when the lock-up time is shortened using a constant current source, does not cause a limitation on current setting.
According to the first feature of the invention, a PLL circuit comprises:
a phase comparator which outputs, as a phase difference signal, a difference in phase between first and second input signals;
a loop filter which smoothens the output of the phase comparator and outputs a smoothened output;
VCO (voltage control oscillator) which receives as input the smoothened voltage output from the loop filter and oscillates at a frequency depending upon said received smoothened voltage;
a mixer which is provided between said VCO and the phase comparator and generates, as the second input signal, a signal of which a target frequency is the frequency of the first input signal;
a detector which detects, based on said phase differential signal output from the phase comparator, whether or not PLL (phase-lock loop) lock is possible, wherein the detector comprises a band pass filter which has a band width corresponding to a difference in frequency between the first and second input signals and receives as input said phase differential signal output from the phase comparator, and a differential pair circuit which receives as input a voltage signal output from the band pass filter and outputs a voltage corresponding to a voltage signal output received from said band pass filter; and
switch means which, when the detector has detected that PLL lock is impossible, switches the loop filter so that the response of the loop filter is enhanced.
According to this construction, when the detector has detected such a state the PLL circuit is unlockable, the switch means switches the loop filter so that the response is enhanced, whereby the input voltage of VCO is rapidly increased. On the other hand, when the PLL circuit is lockable, the loop filter is brought to a usual operation state. By virtue of this, the rise in VCO is rapid, and the lock-up time is shortened. In addition, unnecessary spurious harmonics can be reduced.
According to the second feature of the invention, a PLL circuit comprises:
a current output-type phase comparator which outputs, as a phase difference signal, a difference in phase between first and second input signals;
a loop filter which smoothens the output of the current output-type phase comparator and outputs a smoothened output;
a constant current source for supplying current to the loop filter at a predetermined time;
a detector which detects, based on said phase differential signal output from the phase comparator, whether or not said PLL lock is possible;
a reset switch coupled to said detector, said reset switch connected between the input terminal of the loop filter and the ground and, when PLL (phase-lock loop) lock is possible, is turned off and, when said PLL lock is impossible, is turned on;
VCO (voltage control oscillator) which receives as input the smoothened output voltage from the loop filter and oscillates at a frequency depending upon said received smoothened voltage;
a mixer which is provided between said VCO and the phase comparator and generates, as the second input signal, a signal of which a target frequency is the frequency of the first input signal;
switch means which, when the detector has detected that PLL lock is impossible, turns on the constant current source.
According to this construction, when the detector has detected such a state that the PLL circuit is unlockable, the switch means turns on the constant current source to allow a current to flow from the constant current source to the loop filter, thereby permitting the capacitor of the loop filter to be rapidly charged. On the other hand, when the PLL circuit is lockable, the constant current source is turned off and is separated from the input terminal of the loop filter. By virtue of this, the rise in VCO is rapid, and the lock-up time is shortened. In addition, unnecessary spurious harmonics can be reduced, and there is no limitation on current setting.